Tag: IAR

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IEEE-754 32-bit Single Precision Floating Point Representation

IEEE 754 format for the representation of 32 bit single-precision floating-point numbers
IEEE 754 format for the representation of 32 bit single-precision floating-point numbers

In an ARM Cortex, M4F processor-based microcontroller such as STM32L476vg; the floating-point number is stored in accordance to the IEEE-754.

In the above video, I have written a small code using IAR workbench. When I debugged the program using IAR. I have observed that the floating-point number is converted by the compiler into IEEE 754 format and it is being stored in S# registers of the STM32L476vg. Which are the register present in the FPU(Floating Point Unit) or VFP(Vectored Floating Point) unit.

If you want to go into details, here is the abstract

Abstract: This standard specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming environments. This standard specifies exception conditions and their default handling. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware. For operations specified in the normative part of this standard, numerical results and exceptions are uniquely determined by the values of the input data, sequence of operations, and destination formats, all under user control.

“IEEE Standard for Floating-Point Arithmetic,” in IEEE Std 754-2008 , vol., no., pp.1-70, 29 Aug. 2008, doi: 10.1109/IEEESTD.2008.4610935.

A great tool to have is the online IEEE 754 convertor

https://www.h-schmidt.net/FloatConverter/IEEE754.html

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Subtraction using 2’s complement method

S.N0.DecimalSign MagnitudeOne ComplementTwo Complement
00000000000000
11000100010001
22001000100010
33001100110011
44010001000100
55010101010101
66011001100110
77011101110111
8-010001111=(0000)’+1
=1111 + 1
=0000(discard MSB)
9-110011110=(0001)’ + 1
=(1110) + 1
=1111
10-210101101 =(0010)’ + 1
=(1101) + 1
=1110
11-310111100 =(0011)’ + 1
=(1100) + 1
=1101
12-411001011 =(0100)’ + 1
=(1011) + 1
=1100
13-511011010 =(0101)’ + 1
=(1010) + 1
=1011
14-611101001 =(0110)’ + 1
=(1001) + 1
=1010
15-711111000 =(0111)’ + 1
=(1000) + 1
=1001
16-8(not allowed in 4-bit) (not allowed in 4-bit) =(1000)’+1
=(0111)+1
=1000
Table showing Decimal Numbers representation in sign-magnitude, one complement and two complement

Subtraction using 2’s complement method is performed in microcontroller processors.

To perform subtraction using 2’s complement method we need to do the following steps.

step 1: Find the 2’s complement of subtrahend number.

step 2: Add the 2’s complement of subtrahend to the minuend.

step 3: Check the result for the carry.

If there is carry generated.
Then the result obtained is positive. And there is no further processing needed.

If there is no carry generated.
Then the result obtained is negative. And you have to do 2’s complement of the result obtained.

NOTE:
When doing subtraction using 2’s complement. Pay close attention to the sign of the subtrahend and minuend and the result.

EXAMPLE:

Ques.) 5 – 2 = ?
Ans.) 5 – 2 = 3 (in decimal)

using 2’s complement method
(-2) representation in two’s complement form = 1110

(5) in 2’s complement number = 0101

0101
+ 1110
——-
1 0011 = 3 (by discarding the MSB 1, Here MSB is the carry)
There is a carry generated. So, the number is positive and no further processing is required.
We can discard the carry.

Ques.) -8 – 2 = ? in a 4-bit system
Ans.) -8 – 2 = -10 (in decimal)
Remeberwe have only 4 bit to store the number.
using 2’s complement method
(-2) representation in two’s complement form = 1110

(-8) in 2’s complement number = 1000

1000
+ 1110
——-
1 0110 = 6 (by discarding the MSB 1, Here MSB is the carry)
There is a carry generated. So, the number is positive and no further processing is required.
But, the result obtained is wrong. Because if we add two numbers of the same sign result must be of the same sign. This condition creates an overflow.

Overflow in 2’complement subtraction

When two numbers of the same sign are added together and they produce a result with an opposite sign; An overflow has occurred and the result is not valid.

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IDE Supporting STM32L476-Discovery

An IDE combines a range of different tools which are essential for the development of software. Different IDE from different vendors is available.

Here are the IDE that I have used.

  1. STM CUBE IDE
    website: https://www.st.com/en/development-tools/stm32cubeide.html
    It is distribuited freely by ST. You can use this and it has a good device support and newer devices are quickly added to it. ST uses the eclipse IDE as the base and then they have customized it heavily for the microcontroller development. It also comes with their ST cube MX integrated in it. Which makes development quicker. From the information i have gathered till now it uses gcc as their compiler. Support is available at the forum hosted by ST on thier website.
    They offer support for freeRTOS out of the box.
  2. Keil MDK
    website: https://www2.keil.com/mdk5
    They have a wide support for ARM based devices. You can download the IDE from thier website. It has two version one is the evaluation which limits your code size to 32 Kilo Bytes; but it is good for begineers. The second is the paid option. In both the version all the tools works fine. It is just the code size that puts a limit.
    Keil also host a huge knowledge base on their website. It also has some sample which can be usefull in getting started.
  3. IAR Embedded Workbench for Arm (EWARM)
    website : https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/
    They are also used by the electronic industry. They also has their own compiler which is written for the speed. They have a standard layout and option. They are user friendly. From the information gathered by me they have tested functions only. So it is very standardised set of tool. They also have put a limit on their evualtion IDE of 32 Kilo Byte Code size.